The present invention relates to a circuit and method for outputting data, and more particularly, to a circuit and method capable of outputting data at a high speed.
In order to enhance an operational speed of a synchronous semiconductor memory device such as a synchronous dynamic random access memory (SDRAM) device, data stored in a memory core are read out by N bits in parallel at one time in response to a read command and the data are prefetched before being outputted in series through each output pin DQ. This prefetch scheme can be extended to a 2-bit prefetch scheme where 2-bit data are stored for each output pin DQ in advance as well as a 4-bit prefetch or 8-bit prefetch scheme where 4-bit or 8-bit data are stored in advance.
FIG. 1 illustrates a diagram of a conventional data output circuit. Specially, FIG. 1 shows a diagram of a data output circuit of a synchronous semiconductor memory device reading out data in a 4-bit prefetch scheme for one output pin DQ.
The conventional data output circuit includes an input/output sense amplifying block 101, a storing block 111 and a parallel-to-serial converting block 129.
First parallel data signals DATA1/B to DATA4/B sensed and amplified at bit line sense amplifiers (not shown) are inputted to the input/output sense amplifying block 101 through 4 pairs of main/sub local input/output lines LIO_1/B to LIO_4/B, wherein the input/output sense amplifying block 101 includes a plurality of input/output sense amplifiers 103, 105, 107 and 109. The input/output sense amplifying block 101 amplifies the first parallel data signals DATA1/B to DATA4/B in response to a first strobe signal STRB_1 generated by delaying a column selection signal YI by a certain delay amount and outputs second parallel data signals D1 to D4 to global input/output lines GIO_1 to GIO_4. Since data signals transmitted through one pair of main/sub local input/output lines correspond to data signals transmitted through one global input/output line, each of the first parallel data signals DATA1/B to DATA4/B and the second parallel data signals D1 to D4 may include 4 bits.
The storing block 111 includes a plurality of pass gates 113, 115, 117 and 119 and a plurality of latching elements 121, 123, 125 and 127. The plurality of pass gates 113, 115, 117 and 119 is turned on/off in response to a second strobe signal STRB_2 and transfers the second parallel data signals D1 to D4 transmitted through the global input/output lines GIO_1 to GIO_4 to the plurality of latching elements 121, 123, 125 and 127. The storing block 111 uses the second strobe signal STRB_2 to secure a timing margin between the second parallel data signals D1 to D4 and a signal activating the storing block 111. The second strobe signal STRB_2 may be generated by delaying the first strobe signal STRB_1 using a delay unit (not shown). The delay unit delays the first strobe signal STRB_1 by a delay amount in the transmission of the second parallel data signals D1 to D4 in response to the first strobe signal STRB_1 from the input/output sense amplifying block 101 to the storing block 111.
Since the plurality of latching elements 121, 123, 125 and 127 stores the second parallel data signals D1 to D4 although the plurality of pass gates 113, 115, 117 and 119 is turned off, the parallel-to-serial converting block 129 can sequentially output the second parallel data signals D1 to D4.
The parallel-to-serial converting block 129 outputs the second parallel data signals D1 to D4 in output order determined in response to an output control signal ORDER_CTRL. For instance, in the parallel-to-serial converting block 129, the second parallel data signals D1 to D4 may be outputted in order of D1, D2, D3 and D4 if the output control signal ORDER_CTRL is 00; in order of D4, D1, D2 and D3 if the output control signal ORDER_CTRL is 01; in order of D3, D4, D1 and D2 if the output control signal ORDER_CTRL is 10; and in order of D2, D3, D4 and D1 if the output control signal ORDER_CTRL is 11.
Also, the parallel-to-serial converting block 129 sequentially outputs the second parallel data signals D1 to D4 after an address access time tAA passes from a point of time where a read command is inputted from the outside of the synchronous semiconductor memory device in response to a CAS latency signal CL_CTRL including information for CAS latency CL. The CAS latency CL represents the number of clock cycles required until data signals are outputted to the outside of the synchronous semiconductor memory device after the read command is inputted and it may be set in a mode register set (MRS). The address access time tAA means a time taken until a first data signal is outputted to the outside of the synchronous semiconductor memory device after the read command is inputted. Therefore, if the address access time tAA is 16 ns and one clock cycle is 3 ns, the CAS latency CL may be equal to or greater than 6.
FIG. 2 illustrates a timing diagram of the data output circuit described in FIG. 1 in case the CAS latency CL is 6 and the parallel-to-serial converting block 129 outputs the second parallel data signals D1 to D4 in order of D1, D2, D3 and D4.
If the column selection signal YI is enabled after the read command is inputted, there occurs a potential difference between the main/sub local input/output lines LIO_1/B to LIO_4/B that are precharged to a logic high level when the first parallel data signals DATA1/B to DATA4/B sensed and amplified at the bit line sense amplifiers are loaded onto the 4 pairs of main/sub local input/output lines LIO_1/B to LIO_4/B. The input/output sense amplifying block 101 senses and amplifies the potential difference between the main/sub local input/output lines LIO_1/B to LIO_4/B in response to the first strobe signal STRB_1 and outputs the second parallel data signals D1 to D4 onto the global input/output lines GIO_1 to GIO_4. For instance, if the potential of the first main local input/output line LIO_1 transits to a logic low level, the second parallel data signal D1 of the first global input/output line GIO_1 transits to a logic high level. If the potential of the first sub local input/output line LIO_1B transits to a logic low level, the second parallel data signal D1 of the first global input/output line GIO_1 transits to a logic low level.
The storing block 111 latches the second parallel data signals D1 to D4 in response to the second strobe signal STRB_2. The parallel-to-serial converting block 129 sequentially outputs the second parallel data signals D1 to D4 in order of D1, D2, D3 and D4 after clock cycles corresponding to the CAS latency CL, that is 6, in response to the output control signal ORDER_CTRL.
FIG. 3 illustrates a waveform diagram of the data signals transmitted through the global input/output lines described in FIG. 1.
Although FIG. 1 describes only 4 global input/output lines GIO_1 to GIO_4, in case a synchronous semiconductor memory device has 16 output pins DQ and processes data using a 4-bit prefetch scheme, the semiconductor memory device includes 16*4 global input/output lines. As illustrated in FIG. 3, in case only the data signal transmitted through the global input/output line GIO_1 transits from a logic high level to a logic low level, the coupling may occur between the data signal transmitted through the global input/output line GIO_1 and the data signals transmitted through the global input/output lines GIO_2 and GIO_5 adjacent to the global input/output line GIO_1 that transit from a logic low level to a logic high level, so that the data signal transmitted through the global input/output line GIO_1 may be delayed by a first delay amount DD_1 due to simultaneous switching noise (SSN).
Therefore, in case the second parallel data signal D1 is first outputted from the parallel-to-serial converting block 129, the conventional data output circuit increases the address access time tAA representing an important operational property of the synchronous semiconductor memory device, and thus may deteriorate a high speed operational property of the synchronous semiconductor memory device and erroneously output undesired data signals by the delay of the data signals.